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DESCRIPTION
WM9707 is a high-quality stereo audio CODEC compliant with the AC'97 Revision 2.1 specification. It performs full duplex 18-bit CODEC functions and supports variable sample rates from 8 to 48k samples/s and offers excellent quality with high SNR. Additional features include 3D sound enhancement, line-level outputs, hardware sample rate conversion, master/slave mode operation and SPDIF output. WM9707 is interchangeable with AC'97 CODECs from Wolfson and other suppliers. The WM9707 is fully operable on 3.3V or 5V or mixed 3.3/5V supplies, and is packaged in the industry standard 48-lead TQFP package with 7mm body size.
WM9707
AC'97 Revision 2.1 Audio CODEC with SPDIF Output
AC'97 FEATURES
* * * * * * * * * * * * * * * 3.3V or 5V operation 18-bit stereo CODEC S/N ratio > 95dB Multiple stereo input mixer Mono and stereo volume control 48-lead TQFP package Power management features Very low standby power Variable rate audio (VRA) support Analogue 3D stereo enhancement Line level outputs Supports Rev. 2.1 specified audio sample rates and filtering Master/slave ID selection PC-beep connection when device held reset SPDIF digital output
BLOCK DIAGRAM
VOL/ MUTE VOL/ MUTE KEY: MONO STEREO
VOL/ MUTE VOL/ MUTE
VOL/ MUTE VOL/ MUTE
LINEOUT
LNLVLOUT
MUX
VOL/ MUTE
MONOOUT
STEREO DAC
SRC EAPD
3D
VOL/ MUTE VOL/ MUTE VOL/ MUTE VOL/ MUTE VOL/ MUTE
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WM9707
BITCLK SERIAL I/F SYNC SDATAIN SDATAOUT RESETB SPDIF ENABLE SPDIF
CD LINEIN VIDEO AUX PHONE PCBEEP MIC1 MUX MIC2
VOL RECORD MUX AND MUTE 0dB/ 20dB
STEREO ADC
SRC
MASTER/ SLAVE SELECT
CID
OSC
XTLIN XTLOUT
WOLFSON MICROELECTRONICS plc
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Production Data, June 2006, Rev 4.1
Copyright 2006 Wolfson Microelectronics plc
WM9707 TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 AC'97 FEATURES .................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 ABSOLUTE MAXIMUM RATINGS.........................................................................4 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................5 PIN DESCRIPTION ................................................................................................8 DETAILED TIMING DIAGRAMS ............................................................................9
AC-LINK LOW POWER MODE...................................................................................... 9 COLD RESET ................................................................................................................ 9 WARM RESET............................................................................................................. 10 CLOCK SPECIFICATIONS .......................................................................................... 10 DATA SETUP AND HOLD (50PF EXTERNAL LOAD) ................................................. 11 SIGNAL RISE AND FALL TIMES ................................................................................. 11
SYSTEM INFORMATION .....................................................................................12 DEVICE DESCRIPTION.......................................................................................15
INTRODUCTION.......................................................................................................... 15 3D STEREO ENHANCEMENT..................................................................................... 15 VARIABLE SAMPLE RATE SUPPORT........................................................................ 16 SPDIF DIGITAL AUDIO DATA OUTPUT ..................................................................... 16 GAIN CONTROL REGISTER LOCATION.................................................................... 16 MASTER/SLAVE ID SUPPORT ................................................................................... 17 CONTROL INTERFACE .............................................................................................. 17 AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL................................................. 17 AC-LINK AUDIO OUTPUT FRAME (SDATAOUT) ....................................................... 19 AC-LINK AUDIO INPUT FRAME (SDATAIN) ............................................................... 21 AC-LINK LOW POWER MODE.................................................................................... 23 WAKING UP THE AC-LINK ......................................................................................... 23 SERIAL INTERFACE REGISTER MAP DESCRIPTION .............................................. 24 POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H) .................................. 27 REVISION 2.1 REGISTERS (INDEX 28H T0 58H) ...................................................... 28 VENDOR RESERVED REGISTERS (INDEX 5AH - 7AH)............................................ 29
SERIAL INTERFACE REGISTER MAP ...............................................................31 RECOMMENDED EXTERNAL COMPONENTS ..................................................32
RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 33 RECOMMENDATIONS FOR 3.3V OPERATION.......................................................... 33
PACKAGE DIMENSIONS ....................................................................................34 IMPORTANT NOTICE ..........................................................................................35
ADDRESS:................................................................................................................... 35
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PIN CONFIGURATION
SPDIF ENABLE LNLVLOUTR LNLVLOUTL MONOOUT
37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 LINEOUTR LINEOUTL CX3D2 CX3D1 CAP2 NC NC NC VREFOUT VREF AVSS1 AVDD1 LINEINR
48 DVDD1 XTLIN XTLOUT DVSS1 SDATAOUT BITCLK DVSS2 SDATIN DVDD2 SYNC RESETB PCBEEP 1 2 3 4 5 6 7 8 9 10 11 12
47
NC
46
45
44
43
42
41
40
NC
39
38
PHONE
AUXR
AUXL
VIDEOR
CDL
ORDERING INFORMATION
DEVICE WM9707SCFT/V WM9707SCFT/RV Note: Reel quantity = 2,200 TEMPERATURE RANGE 0 to 70oC 0 to 70oC PACKAGE 48-lead TQFP (Pb-free) 48-lead TQFP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL2 MSL2 PEAK SOLDERING TEMPERATURE 260oC 260oC
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CDGND
LINEINL
VIDEOL
MIC1
CDR
MIC2
AVDD2
CID
AVSS2
SPDIF
EAPD
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature Note: 1. The digital supply voltage (DVDD) must always be less than or equal to the analogue supply voltage (AVDD). MIN -0.3V -0.3V DVSS -0.3V AVDD -0.3V 0oC -65 C
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MAX +7V +7V DVDD +0.3V AVDD +0.3V +70oC +150 C
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WM9707 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Digital ground Analogue ground Difference DVSS to AVSS Analogue supply current Digital supply current Standby supply current (all PRs set) Analogue supply current Digital supply current Standby supply current (all PRs set) Note: 1. Both supplies should be powered on and off at the same time. DVDD, AVDD = 5V DVDD, AVDD = 5V DVDD, AVDD = 5V DVDD, AVDD = 3.3V DVDD, AVDD = 3.3V DVDD, AVDD = 3.3V SYMBOL DVDD1, DVDD2 AVDD1, AVDD2 DVSS1, DVSS2 AVSS1, AVSS2 -0.3 TEST CONDITIONS MIN -10% -10% TYP 3.3 to 5.0 3.3 to 5.0 0 0 0 30 16 10 16 11 10
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MAX +10% +10%
UNIT V V V V
+0.3
V mA mA uA mA mA uA
ELECTRICAL CHARACTERISTICS
Test Characteristics: AVDD = 5V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated DVDD = 3.3V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated PARAMETER Input LOW level Input HIGH level Output LOW Output HIGH Input level Output level Reference Levels Reference input/output CAP2 impedance Mixer reference MIC reference MIDBUFF current sink (pins VREF and VREFOUT) MIDBUFF current source (pins VREF and VREFOUT) MIDBUFF current source (pins VREF and VREFOUT) MIDBUFF current sink (pins VREF and VREFOUT) VREF VREFOUT AVDD = 5V AVDD = 5V AVDD = 3.3V AVDD = 3.3V -5 5 CAP2 2/5 AVDD AVDD/2 75 Buffered CAP2 Buffered CAP2 -15 15 10 -10 3/5 AVDD V k V V mA mA mA mA SYMBOL VIL VIH VOL VOH IOL = 1mA IOL = 1mA Minimum input impedance = 10k Into 10k load 0.90 x VDD AVSS -100mV AVSS +300mV Near rail to rail AVDD +100mV AVDD -300mV TEST CONDITIONS MIN AVSS -0.3 2.2 TYP MAX 0.8 AVDD +0.3 0.10 x VDD UNIT V V V V V V
Digital Logic Levels (DVDD = 3.3 or 5.0V)
Analogue I/O Levels (Input Signals on any inputs, Outputs on LINEOUT L, R and MONOOUT)
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Test Characteristics: AVDD = 5V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated DVDD = 3.3V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated PARAMETER SNR A-weighted (Note 1) Full scale output voltage THD Frequency response Transition band Stop band Out of band rejection Spurious tone reduction PSRR SNR A-weighted (Note 1) ADC input for full scale output THD Frequency response Transition band Stop band Stop band rejection PSRR SNR CD path A-weighted (Note 1) SNR Other paths A-weighted (Note 1) Maximum input voltage Maximum output voltage on LINEOUT THD Frequency response (+/-1dB) Input impedance (CD inputs) Input impedance (other mixer inputs) Input impedance MIC inputs PSRR SNR A-weighted (Note 1) Full scale output voltage THD Frequency response Transition band Stop band Out of band rejection Spurious tone reduction PSRR 20 to 20kHz VREF = 1.65V -3dBFS input 20 19,200 28,800 -40 -100 40 At any gain At max gain At 0db gain At max gain At 0db gain 20 to 20kHz DAC Circuit Specifications (AVDD = 3.3V) 48kHz sampling 92 0.7 -85 19,200 28,800 10 50 10 55 0dBv input 20 to 20kHz 90 85 AVSS 1.0 74 20 15 20 100 30 110 50 Mixer Circuit Specifications (AVDD = 5V) 48kHz sampling 100 95 1.0 1.8 -90 20,000 AVDD VREF = 2.5V -6dBv input 74 20 19,200 28,800 -74 40 20 to 20kHz 75 ADC Circuit Specifications (AVDD = 5V) 48kHz sampling 90 1.0 -85 19,200 28,800 VREF = 2.5V -3dBfs input 74 (0.02%) 20 19,200 28,800 -40 -100 40 SYMBOL TEST CONDITIONS MIN 85 TYP 95 1.0 -90 19,200 28,800 MAX
Production Data
UNIT dBv Vrms dBv Hz Hz Hz dB dB dB dB Vrms dB Hz Hz Hz dB dB dB dB Vrms Vrms dB Hz k k k k k dB dB Vrms dB Hz Hz Hz dB dB dB
DAC Circuit Specifications (AVDD = 5V) 48kHz sampling
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Test Characteristics: AVDD = 5V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated DVDD = 3.3V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated PARAMETER SNR A-weighted (Note 1) ADC input for full scale output THD Frequency response Transition band Stop band Stop band rejection PSRR SNR CD path A-weighted (Note 1) SNR Other paths A-weighted (Note 1) Maximum input voltage Maximum output voltage on LINEOUT THD (Note 2) Frequency response (+/-1dB) Input impedance (CD inputs) Input impedance (other Mixer inputs) Input impedance MIC inputs PSRR Clock Frequency Range Crystal clock BITCLK frequency SYNC frequency Notes: 1. 2. 24.576 12.288 48.0 At any gain At max gain At 0db gain At max gain At 0db gain 20 to 20kHz -3.6dBv input 20 15 20 100 30 110 50 20 to 20kHz Mixer Circuit Specifications (AVDD = 3.3V) 48kHz sampling 95 90 0.6 1.2 85 20,000 VREF = 1.65V -6dBv input 20 19,200 28,800 -74 40 SYMBOL TEST CONDITIONS MIN TYP 85 0.7 80 19,200 28,800 MAX
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UNIT dB Vrms dB Hz Hz Hz dB dB dB dB Vrms Vrms dBv Hz k k k k k dB MHz MHz kHz
ADC Circuit Specifications (AVDD = 3.3V) 48kHz sampling
SNR is the ratio of 0dB signal output to the output level with no signal, measured A-weighted over a 20Hz to 20kHz bandwidth. Inputs are scaled for AVDD eg; 0dBv at 5.0V is equivalent to -3.6dBv at 3.3V.
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WM9707 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME DVDD1 XTLIN XTLOUT DVSS1 SDATAOUT BITCLK DVSS2 SDATAIN DVDD2 SYNC RESETB PCBEEP PHONE AUXL AUXR VIDEOL VIDEOR CDL CDGND CDR MIC1 MIC2 LINEINL LINEINR AVDD1 AVSS1 VREF VREFOUT NC NC NC CAP2 CX3D1 CX3D2 LINEOUTL LINEOUTR MONOOUT AVDD2 LNLVLOUTL NC LNLVLOUTR AVSS2 NC SPDIF ENABLE CID NC EAPD SPDIF Digital output Digital output Digital input Digital input Analogue output Supply Analogue input Analogue output Analogue input Analogue output Analogue output Analogue output Supply Analogue output Supply Digital input Digital output Supply Digital input Digital output (master) Digital input (slave) Supply Digital output Supply Digital input Digital input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Supply Supply Analogue output Analogue output TYPE Digital positive supply DESCRIPTION
Production Data
Clock crystal connection or clock input (XTAL not used) Clock crystal connection Digital ground supply Serial data input Serial interface clock output to AC'97 controller or input from AC'97 master CODEC Digital ground supply Serial data output to AC'97 controller Digital positive supply Serial interface sync pulse from AC'97 controller NOT reset input (active low, resets registers) Mixer input, typically for PCBEEP signal Mixer input, typically for PHONE signal Mixer input, typically for AUX signal Mixer input, typically for AUX signal Mixer input, typically for VIDEO signal Mixer input, typically for VIDEO signal Mixer input, typically for CD signal CD input common mode reference (ground) Mixer input, typically for CD signal Mixer input with extra gain if required Mixer input with extra gain if required Mixer input, typically for LINE signal Mixer input, typically for LINE signal Analogue positive supply Analogue ground supply, chip substrate Buffered CAP2 Reference for microphones; buffered CAP2 No internal connection No internal connection No internal connection Reference input/output; pulls to midrail if not driven Output pin for 3D difference signal Input pin for 3D difference signal Main analogue output for left channel Main analogue output for right channel Main mono output Analogue positive supply Left channel line level output No internal connection Right channel line level output Analogue ground supply, chip substrate No internal connection SPDIF ENABLE (internal pull-down) Master/slave ID select (internal pull-up), Hi = master No internal connection External amplifier powerdown/GPO SPDIF digital audio data output
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WM9707 DETAILED TIMING DIAGRAMS
Test Characteristics: AVDD = 5V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated. DVDD = 3.3V, GND = 0V ..............TA = 0oC to +70oC, unless otherwise stated. All measurements are taken at 10% to 90% VDD, unless otherwise stated. All the following timing information is guaranteed, not tested.
Production Data
AC-LINK LOW POWER MODE
SLOT 1 SYNC
SLOT 2
BITCLK
SDATAOUT
WRITE TO 0X20
DATA PR4
DON'T CARE
tS2_PDOWN SDATAIN
Figure 1 AC-Link Powerdown Timing PARAMETER End of slot 2 to BITCLK SDATIN low SYMBOL tS2_PDOWN MIN TYP MAX 1.0 UNIT s
COLD RESET
tRST_LOW RESETB tRST2CLK
BITCLK
Figure 2 Cold Reset Timing PARAMETER RESETB active low pulse width RESETB inactive to BITCLK startup delay SYMBOL tRST_LOW tRST2_CLK MIN 1.0 162.8 TYP MAX UNIT s ns
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WARM RESET
tSYNC_HIGH SYNC tSYNC2CLK
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BITCLK
Figure 3 Warm Reset Timing PARAMETER SYNC active high pulse width SYNC inactive to BITCLK startup delay SYMBOL tSYNC_HIGH tSYNC2_CLK 162.4 MIN TYP 1.3 MAX UNIT s ns
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC tSYNC_PERIOD
Figure 4 Clock Specifications (50pF External Load) Note: Worst case duty cycle restricted to 40/60. PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width ( See Note) BITCLK low pulse width ( See Note) SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 32.56 32.56 40.7 40.7 48.0 20.8 1.3 19.5 tCLK_PERIOD SYMBOL MIN TYP 12.288 81.4 750 48.84 48.84 MAX UNIT MHz ns ps ns ns kHz s s s
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DATA SETUP AND HOLD (50pF EXTERNAL LOAD)
tSETUP BITCLK tHOLD SYNC SDATAOUT
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Figure 5 Data Setup and Hold (50pF External Load) Note: Setup and hold time parameters for SDATAIN are with respect to AC'97 Controller. PARAMETER Setup to falling edge of BITCLK Hold from falling edge of BITCLK SYMBOL tSETUP tHOLD MIN 15.0 5.0 TYP MAX UNIT ns ns
SIGNAL RISE AND FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Figure 6 Signal Rise and Fall Times (50pF External Load) PARAMETER BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time SYMBOL triseCLK tfallCLK triseSYNC tfallSYNC triseDIN triseDIN triseDOUT tfallDOUT MIN 2 2 2 2 2 2 2 2 TYP MAX 6 6 6 6 6 6 6 6 UNIT ns ns ns ns ns ns ns ns
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CX3D1 CX3D2
BITCLK SYNC (6) EAPD (47) CID (45)
2 x 18 bit
SDATA SDOUT IN OUT RESETB DVDD1&2 (1) (9) (4) (7) DVSS1&2 (8) (5) (11)
DACCLK
(33) (10) (34)
WM9707
Serial Interface
DAC Audio Data loopback (reg 20h) DAC LADC DATA RADC DATA Programmable IO: supports I2S outputs for surround channels ADC SPDIF (48) SPDIF ENABLE (44)
Digital Sigma Delta Modulators DAC Interpolation Filters
SRC control reg 2Ch
Variable Rate Audio Support
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DAC PGA PGA Reg 18h POP (20h) SRC control reg 32h
SYSTEM INFORMATION
Figure 7 Functional Block Diagram
ADC Decimation filters
ADCCLK FRONT VOLUME WM '3-D' ENHANCE Reg 22h MIXER PGA L R PGA Reg 72h PGA Reg 02h (typ) LINE VOLUME PGA Reg 04h Mono Mux MONO VOLUME PGA Reg 06h ADCNDAC Reg5Ah L R MONOOUT (37) LNLVLOUTL (39) LNLVLOUTR (41) LINEOUTL (35) LINEOUTR (36) PGA Reg 12h ADCREF
Multibit DAC and Filter DACR PCM DACs Multibit DAC and Filter DACL
DACREF
CDL (18)
CDGND (19)
CDR (20)
LINEINL (23)
PGA Reg 10h
LINEINR (24)
VIDEOL(16)
PGA Reg 14h
VIDEOR (17)
AUXL (14)
WM9707 AC97 rev2.1 Codec
PR0 ADC EN POWER ENABLE reg 26h PR1 DAC EN PR2 MIX EN PR3 REF EN PR4 LNK EN PR5 CLK EN EN EAPD
ADC PGA
Analogue Sigma Delta Modulator
RECORD MUX Reg 1Ah PGA Reg 1Ch ADCCLK
PGA Reg 16h
AUXR (15)
Analogue Sigma Delta Modulator
XTLIN (2) ADCCLK DACCLK CLOCK GENERATOR XTLOUT (3)
PHONE (13)
PGA Reg 0Ch
PCBEEP(12)
PGA Reg 0Ah
AVDD1 (25) MIXREF AVDD2 (38) DACREF ADCREF AVSS2 (42) AVSS1 (26) CAP2 (32) VREFOUT (28) VREF (27)
MIC1 (21) +20dB PGA Reg 0Eh
Mic
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MIC2 (22)
Mux
Production Data
12
WM9707
MIC1 MIC2 PCBEEP CD, VIDEO, AUX, LINEINL/R PHONE
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22
21
12
13
35
LINEOUTL/R
36
RESET
AC'97 DIGITAL CONTROLLER
BITCLK SYNC SDATAIN SDATAOUT
6 10 8 5
WM9707
39 41
37 48
CID
45 AUDIO SPDIF TRANSFORMER CIRCUIT
Figure 8 Revision 2.1 Compliant 2-Channel CODEC
Figure 9 WM9707 in a 4 Channel System
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{
11
LNLVLOUTL/R
MONO_OUT SPDIF OUTPUT
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WM9707
SDATAOUT BITCLK SDATAIN SYNC RESETB
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PC I/O CHIPSET OR AC'97 CONTROLLER
Option of using RESETB or SDATAIN to disable NB CODEC when docked.
LINEOUTL SDATAOUT BITCLK SDATAIN WM9707 SYNC RESETB
CID
SDATAOUT BITCLK SDATAIN WM9707 SYNC RESETB
LINEOUTR
ID=0
ID=0
NOTEBOOK/ LAPTOP
If pin CID is not driven then CODEC ID defaults to 0. When docked CID is pulled low making CODEC a 'slave' (1) stopping BITCLK
DOCKING STATION
Figure 10 WM9707 in a Docking Station System
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WM9707 DEVICE DESCRIPTION
INTRODUCTION
The WM9707 is fully compliant with Revision 2.1 of the AC'97 specification.
Production Data
The WM9707 comprises a stereo 18-bit CODEC, (that is, 2 ADCs and 2 DACs) a comprehensive analogue mixer with 4 sets of stereo inputs, phone, 2 microphone, and PC-beep inputs. Additionally, on-chip reference generation circuits generate the necessary bias voltages for the device, and a bidirectional serial interface allows transfer of control data and DAC and ADC words to and from the AC'97 controller. The WM9707 supports 18-bit resolution within the DAC and ADC functions, but the AC'97 serial interface specification allows any word length up to 20-bits to be written to, or read from, the AC'97 CODEC. These words are MSB justified, and any LSBs not used will simply default to 0. Normally it is anticipated that 16-bit words will be used in most PC type systems. Therefore, for the DAC, 16-bit words will be downloaded into the CODEC from the controller, along with padding of 0s to make the 16-bit word up to 20-bit length. In this case, the WM9707 will process the 16-bit word along with 0 padding bits in the 2 LSB locations (to make 18-bit). At the ADC output, WM9707 will provide an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC'97 controller will then ignore the 4 LSBs of the 20-bit word. When the WM9707 is interrogated at Register 00h, it responds indicating it is an 18-bit device. The WM9707 has the ADC and DAC functions implemented using oversampled, or sigma-delta converters, and uses on-chip digital filters to convert these 1-bit signals to and from the 48ks/s 16/18bit PCM words that the AC'97 controller requires. The digital parts of the device are powered separately from the analogue to optimise performance, and 3.3V digital and 5V analogue supplies may be used on the same device to further optimise performance. Digital IOs are 5V tolerant when the analogue supplies are 5V, so the WM9707 may be connected to a controller running on 5V supplies, but use 3.3V for the digital section of WM9707. WM9707 is also capable of operating with a 3.3V supply only (digital and analogue). An internally generated midrail reference is provided at pin CAP2 which is used as the chip reference. This pin should be heavily decoupled. Refer to Figure 18 for more details. The WM9707 is not limited to PC-only applications. The ability to power down sections of the device selectively, and the option to choose alternative master clock, and hence sample rates, means that many alternative applications in areas such as telecomms, may be anticipated. Additional features added to the Intel AC'97 specification, such as the EAPD (External Amplifier Powerdown) bit, internal connection of PC-beep to the outputs in the case where the device is reset, are supported, along with optional features such as variable sample rate support and SPDIF output.
3D STEREO ENHANCEMENT
This device contains a stereo enhancement circuit, designed to optimise the listening experience when the device is used in a typical PC operating environment. That is, with a pair of speakers placed either side of the monitor with little spatial separation. This circuit creates a difference signal by differencing left and right channel playback data, then filters this difference signal using lowpass and highpass filters whose time constants are set using external capacitors connected to the CX3D pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass poles at about 100Hz and 1kHz respectively. This frequency band corresponds to the range over which the ear is most sensitive to directional effects. The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to Register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h is optimum. The user interface would most typically use a slider type of control to allow the user to adjust the level of enhancement to suit the program material. Bit D13 3D in Register 20h is the overall 3D enable bit. The capability Register 00h reads back the value 11000 in bits D14 to D10. This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement. Note that the external capacitors setting the filtering poles applied to the difference signal may be adjusted in value, or even replaced with a direct connection between the pins. If such adjustments are made, then the amount of difference signal fed back into the main signal paths may be significant, and can cause large signals which may limit, distort, or overdrive signal paths or speakers. Adjust these values with care, to select the preferred acoustic effect.
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Production Data There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied (if the signals are in phase and of the same amplitude). Signals from the PCM DAC channels can have stereo enhancement applied. It can also be bypassed if desired. This control is enabled by setting the POP bit in Register 20h.
VARIABLE SAMPLE RATE SUPPORT
The DACs and ADCs on this device support all the recommended sample rates specified in the Intel Revision 2.1 specification for audio rates. The default rate is 48ks/s. If alternative rates are selected and variable rate audio is enabled (Register 2Ah, bit 0), the AC'97 interface continues to run at 48k words per second, but data is transferred across the link in bursts such that the net sample rate selected is achieved. It is up to the AC'97 Revision 2.1 compliant controller to ensure that data is supplied to the AC link, and received from the AC link, at the appropriate rate. The device supports on demand sampling. That is, when the DAC signal processing circuits need another sample, a sample request is sent to the controller which must respond with a data sample in the next frame it sends. For example, if a rate of 22.05ks/s is selected, on average the device will request a sample from the controller every other frame, for each of the stereo DACs. Note that if an unsupported rate is written to one of the rate registers, the rate will default to the nearest rate supported. The Register will then respond when interrogated with the supported rate the device has defaulted to. The left and right channels of the ADCs and DACs always sample at the same rate. AUDIO SAMPLE RATE (HZ) 8000 11025 16000 22050 32000 44100 48000 CONTROL VALUE D15-D0 (HEX) 1F40 2B11 3E80 5622 7D00 AC44 BB80
Table 1 Variable Sample Rates Supported
SPDIF DIGITAL AUDIO DATA OUTPUT
Pin 48 may be used to output the PCM DAC playback data in SPDIF (IEC958) digital data format. In order to enable this output, bit SPDF in Register 5Ch should be set or pin 44 pulled high. Additionally, a bit SCMS in Register 5Ch may also be set, which removes the copyright flag in the IEC958 data, allowing serial copy protect mechanisms to be implemented. Note that this data output will only operate at the SYNCH rate and so only supports 48ks/s operation. The PCM DACs continue to function normally when SPDIF output is enabled.
GAIN CONTROL REGISTER LOCATION
PGA DAC Mixer Volume CONTROL REGISTER 18h 72h 02h MUTE DEFAULT Muted (bit-15) Not-muted (bit-15) Muted (15)
Table 2 Gain Control Register Location
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MASTER/SLAVE ID SUPPORT
Production Data
WM9707 supports operation as either a master or a slave CODEC. Configuration of the device as either a master or as a slave, is selected by tying the CID pin 45 on the package. Fundamentally, a device identified as a master (ID = 0) produces BITCLK as an output, whereas a slave (any other ID) must be provided with BITCLK as an input. This has the obvious implication that if the master device on an AC link is disabled, the slave devices cannot function. The AC'97 Revision 2.1 specification defines that the CID pin has inverting sense, and are provided with internal weak pull ups. Therefore, if no connections are made to the CID pin, then the pin pulls hi and an ID = 0 is selected, i.e. master. External connects to ground will select other IDs. PIN 45 CID NC Ground Table 3 ID Selection ID SELECTED 0 1 MASTER OR SLAVE Master Slave BITCLK Output Input
CONTROL INTERFACE
A digital interface has been provided to control the WM9707 and transfer data to and from it. This serial interface is compatible with the Intel AC'97. The main control interface functions are: * * * Control of analogue gain and signal paths through the mixer Bi-directional transfer of ADC and DAC words to and from AC'97 controller Selection of Powerdown down modes.
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
The WM9707 incorporates a 5-pin digital serial interface that links it to the AC'97 controller. AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams, as well as control Register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. With a minimum required DAC and ADC resolution of 16-bits, AC'97 may also be implemented with 18 or 20-bit DAC/ADC resolution, given the headroom that the AC-link architecture provides. The WM9707 provides support for 18-bit operation.
SLOT NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
TAG
SDATAOUT
CODEC ID
CMD ADR
CMD DATA
PCM LEFT
PCM RIGHT
RSRVD
PCM CENTRE
PCM L SURR
PCM R SURR
PCM LFE
RSRVD PCM L (n+1)
RSRVD PCM R (n+1)
RSRVD PCM C (n+1)
SDATAIN
TAG
STATUS ADDR
STATUS DATA
PCM LEFT
PCM RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
SLOTREQ 3-12
DATA PHASE TAG PHASE
Figure 11 AC'97 Standard Bi-Directional Audio Frame
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TAG PHASE DATA PHASE 20.8S (48kHz) SYNC
12.288MHz 81.4ns
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BITCLK
SDATAOUT
VALID FRAME
SLOT(1)
SLOT(2)
SLOT(12)
'0'
(ID1)
(ID0)
19 SLOT (1)
0
19 SLOT (2)
0
19 SLOT (3)
0
19 SLOT (12)
0
END OF PREVIOUS AUDIO FRAME
TIME SLOT 'VALID' BITS ('1' = TIME SLOT CONTAINS VALID PCM DATA)
Figure 12 AC-link Audio Output Frame The datastreams currently defined by the AC'97 specification include: PCM playback - 2 output slots PCM record data - 2 input slots Control - 2 output slots Status - 2 input slots Optional modem line CODEC output 1 output slot Optional modem line CODEC input - 1 input slot Optional dedicated microphone input 1 input slot 2-channel composite PCM output stream 2-channel composite PCM input stream Control Register write port Control Register read port Modem line CODEC DAC input stream Modem line CODEC ADC output stream Dedicated microphone input stream in support of stereo AEC and/or other voice applications.
Synchronisation of all AC-link data transactions is signalled by the WM9707 controller. The WM9707 drives the serial bit clock onto AC-link, which the AC'97 controller then qualifies with a synchronisation signal to construct audio frames. SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BITCLK). BITCLK, fixed at 12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The receiver of AC-link data, (WM9707 for outgoing data and AC'97 controller for incoming data), samples each serial bit on the falling edges of BITCLK. The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the data, (the WM9707 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0s during that slot's active time. SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that the WM9707 be implemented as a static design to allow its register contents to remain intact when entering a power savings mode.
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AC-LINK AUDIO OUTPUT FRAME (SDATAOUT)
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The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the WM9707's DAC inputs, and control registers. As briefly mentioned earlier, each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol infrastructure.
OUTPUT TAG SLOT (16-BITS)
Bit (15) Bit (14) Bit (13) Bit (12:3) Bit 2 Bit (1:0) Frame Valid Slot 1 Valid Command Address bit Slot 2 Valid Command Data bit Slot 3-12 Valid bits as defined by AC'97 Reserved 2-bit Message ID field (Set to 0) (00 reserved for Primary; 01 indicates Secondary) (Primary CODEC only) (Primary CODEC only)
Within slot 0 the first bit is a global bit (SDATAOUT slot 0, bit 15) which flags the validity for the entire audio frame. If the Valid Frame bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. The next 12-bit positions sampled by the WM9707 indicate which of the corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-link at its fixed 48kHz audio frame rate. Figure 12 illustrates the time slot based AC-link protocol. When the CODEC is a slave device, bits 14 and 13 are not used to validate data in slots 1 and 2. Instead, if the message ID bits (1:0) match the CODEC ID then the address is valid and bit 19 from slot 1 then indicates if slot 2 is valid.
WM9707 SAMPLES SYNC ASSERTION HERE
SYNC
WM9707 SAMPLES FIRST SDATAOUT BIT OF FRAME HERE
BITCLK
SDATAOUT
VALID FRAME
SLOT (1)
SLOT (2)
END OF PREVIOUS AUDIO FRAME
Figure 13 Start of an Audio Output Frame A new audio output frame begins with a low to high transition of SYNC as shown in Figure 13. SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK, the WM9707 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BITCLK, AC'97 transitions SDATAOUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the WM9707 on the following falling edge of BITCLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. Baseline AC'97 specified audio functionality MUST ALWAYS sample rate convert to and from a fixed 48ks/s on the AC'97 controller. This requirement is necessary to ensure that interoperability between the AC'97 controller and the WM9707, among other things, can be guaranteed by definition for baseline specified AC'97 features. SDATAOUT's composite stream is MSB justified (MSB first) with all non-valid slot bit positions stuffed with 0s by the AC'97 controller. In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC'97 controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.
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Production Data As an example, consider an 8-bit sample stream that is being played out to one of the WM9707's DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit positions, which are stuffed with 0s by the AC'97 controller. This ensures that regardless of the resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least significant bits. When mono audio sample streams are output from the AC'97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data.
SLOT 1: COMMAND ADDRESS PORT
The command port is used to control features, and monitor status for the WM9707 functions including, but not limited to, mixer settings, and power management (refer to the Serial Interface Register Map). The control interface architecture supports up to 64, 16-bit read/write registers, addressable on even byte boundaries. Only the even Registers (00h, 02h, etc.) are valid. Odd register read/write will have no effect on the WM9707. Audio output frame slot 1 communicates control register address, and read/write command information to the WM9707.
COMMAND ADDRESS PORT BIT ASSIGNMENTS
Bit (19) Bit (18:12) Bit (11:0) Read/write command (1 = read, 0 = write) Control register index (64 16-bit locations, addressed on even byte boundaries) Reserved (stuffed with 0s)
The first bit (MSB) sampled by the WM9707 indicates whether the current control transaction is a read or write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC'97 controller.
SLOT 2: COMMAND DATA PORT
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (As indicated by slot 1, bit 19). Bit (19:4) Bit (3:0) Control register write data (stuffed with 0s if current operation is a read) Reserved (stuffed with 0s)
If the current command port operation is a read then the entire time slot must be stuffed with 0s by the AC'97 controller.
SLOT 3: PCM PLAYBACK LEFT CHANNEL
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical Games Compatible PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0s.
SLOT 4: PCM PLAYBACK RIGHT CHANNEL
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical Games Compatible PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0s.
SLOT 5: OPTIONAL MODEM LINE CODEC
Audio output frame slot 5 contains the MSB justified modem DAC input data. This optional AC'97 feature is not supported in the WM9707, and if data is written to this location it is ignored. This may be determined by the AC'97 controller interrogating the WM9707 Vendor ID registers.
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SLOTS 6 TO 9: SURROUND SOUND DATA
Audio output frame slots 6 to 9 are used to send surround sound data.
Production Data
SLOTS 10 AND 11: LINE2 AND HANDSET DAC
These data slots are not supported.
SLOT 12: GPIO CONTROL
These data slots are not supported.
AC-LINK AUDIO INPUT FRAME (SDATAIN)
TAG PHASE DATA PHASE 20.8S (48kHz) SYNC
12.288MHz 81.4ns
BITCLK
SDATAIN
CODEC READY
SLOT(1)
SLOT(2)
SLOT(12)
'0'
'0'
'0'
19 SLOT (1)
0
19 SLOT (2)
0
19 SLOT (3)
0
19 SLOT (12)
0
END OF PREVIOUS AUDIO FRAME
TIME SLOT 'VALID' BITS ('1' = TIME SLOT CONTAINS VALID PCM DATA)
Figure 14 AC-link Audio Input Frame The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. As is the case for audio output frame, each AC-link audio input frame consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol infrastructure. Within slot 0 the first bit is a global bit (SDATAIN slot 0, bit 15) which flags whether the WM9707 is in the CODEC Ready state or not. If the CODEC Ready bit is a 0, this indicates that the WM9707 is not ready for normal operation. This condition is normal following the desertion of power on reset for example, while the WM9707's voltage references settle. When the AC-link CODEC Ready indicator bit is a 1, it indicates that the AC-link and the WM9707 control and status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control/Status Register to determine exactly which subsections, if any, are ready. Prior to any attempts at putting the WM9707 into operation the AC'97 controller should poll the first bit in the audio input frame (SDATAIN slot 0, bit 15) for an indication that the WM9707 has gone CODEC Ready. Once the WM9707 is sampled CODEC Ready then the next 12 bit positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. Figure 14 illustrates the time slot based AC-link protocol. There are several subsections within the WM9707 that can independently go busy/ready. It is the responsibility of the WM9707 controller to probe more deeply into the WM9707 register file to determine which the WM9707 subsections are actually ready.
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WM9703 SAMPLES SYNC ASSERTION HERE
Production Data
SYNC
AC'97 CONTROLLER SAMPLES FIRST SDATA_IN BIT OF FRAME HERE
BITCLK
SDATAIN
CODEC READY
SLOT (1)
SLOT (2)
END OF PREVIOUS AUDIO FRAME
Figure 15 Start of an Audio Input Frame A new audio input frame begins with a low to high transition of SYNC as shown in Figure 15. SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK, AC'97 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BITCLK, AC'97 transitions SDATAIN into the first bit position of slot 0 ("CODEC Ready" bit). Each new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the AC'97 Controller on the following falling edge of BITCLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. SDATAIN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the WM9707. SDATAIN should be sampled on the falling edges of BITCLK.
SLOT 1: STATUS ADDRESS PORT
The status port is used to monitor status for the WM9707 functions including, but not limited to, mixer settings, and power management. Audio input frame slot 1 echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the WM9707 during slot 0).
STATUS ADDRESS PORT BIT ASSIGNMENTS:
Bit (19) Bit (18:12) Bit (11:2) Bit (1:0) RESERVED (stuffed with 0s) Control register index (echo of register index for which data is being returned) Variable sample rate SLOTREQ bits. RESERVED (stuffed with 0s)
The first bit (MSB) generated by the WM9707 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address. The next 10 bits support the AC'97 Rev 2.1 variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by AC'97.
SLOT 2: STATUS DATA PORT
The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3:0) Control register read data (stuffed with 0s if tagged invalid by WM9701) RESERVED (stuffed with 0s)
If slot 2 is tagged invalid by the WM9707, then the entire slot will be stuffed with 0s by the WM9707.
SLOT 3: PCM RECORD LEFT CHANNEL
Audio input frame slot 3 is the left channel output of the WM9707's input Mux, post-ADC. The WM9707 sends out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot.
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SLOT 4: PCM RECORD RIGHT CHANNEL
Production Data
Audio input frame slot 4 is the right channel output of the WM9707's input Mux, post-ADC. The WM9707's ADCs can be implemented to support 16, 18, or 20-bit resolution. The WM9707 ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot.
SLOT 5: OPTIONAL MODEM LINE CODEC
Not supported by WM9707.
SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA
Not supported by WM9707.
SLOTS 7 TO 12: RESERVED
Audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by the WM9707.
AC-LINK LOW POWER MODE
The AC-link signals can be placed in a low power mode. When the WM9707's Powerdown Register 26h, is programmed to the appropriate value, both BITCLK and SDATAIN will be brought to, and held at a logic low voltage level. BITCLK and SDATAIN are transitioned low immediately following the decode of the write to the Powerdown Register 26h with PR4. When the AC'97 controller driver is at the point where it is ready to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. At this point in time it is assumed that all sources of audio input have also been neutralised. The AC'97 controller should also drive SYNC and SDATAOUT low after programming the WM9707 to this low power, halted mode. Once the WM9707 has been instructed to halt BITCLK, a special wake up protocol must be used to bring the AC-link to the active mode since normal audio output and input frames can not be communicated in the absence of BITCLK.
WAKING UP THE AC-LINK
There are 2 methods for bringing the AC-link out of a low power, halted mode. Regardless of the method, it is the AC'97 controller that performs the wake up task. AC-link protocol provides for a Cold WM9707 Reset, and a Warm WM9707 Reset. The current Powerdown state would ultimately dictate which form of WM9707 reset is appropriate. Unless a cold or register reset (a write to the Reset Register 00h) is performed, wherein the WM9707 registers are initialised to their default values, registers are required to keep state during all Powerdown modes. Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the Powerdown was triggered. When AC-link powers up it indicates readiness via the CODEC Ready bit (input slot 0, bit 15).
COLD WM9707 RESET
A cold reset is achieved by asserting RESETB for the minimum specified time (1s). By driving RESETB low, BITCLK, and SDATAOUT will be activated, or re-activated as the case may be, and all the WM9707 control registers will be initialised to their default power on reset values. RESETB is an asynchronous WM9707 input.
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WARM WM9707 RESET
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A warm WM9707 reset will re-activate the AC-link without altering the current WM9707 register values. A warm reset is signalled by driving SYNC high for a minimum of 1s in the absence of BITCLK. Within normal audio frames SYNC is a synchronous input. In the absence of BITCLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the WM9707. The WM9707 will not respond with the activation of BITCLK until SYNC has been sampled low again by the WM9707. This will preclude the false detection of a new audio frame.
SERIAL INTERFACE REGISTER MAP DESCRIPTION
(See Table 17) The serial interface bits perform control functions described as follows: The register map is fully specified by the AC'97 specification, and this description is simply repeated below, with optional unsupported features omitted.
RESET REGISTER (INDEX 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the ID code of the part, indication of modem support (not supported by the WM9707) and a code for the type of 3D stereo enhancement. The ID decodes the capabilities of the WM9707 based on the following: BIT FUNCTION VALUE ON WM9707 (BINARY) 0 0 0 0 1 0 1 0 1 0 11000
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 SE4...SE0
Dedicated Mic PCM in channel Modem line CODEC support Bass and treble control Simulated stereo (mono to stereo) Headphone out support Loudness (bass boost) support 18-bit DAC resolution 20-bit DAC resolution 18-bit ADC resolution 20-bit ADC resolution Wolfson Microelectronics 3D enhancement
Table 4 Reset Register Function Note that the WM9707 defaults to indicate 18-bit compatibility.
PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)
These registers manage the output signal volumes. Register 02h controls the stereo master volume (both right and left channels), Register 04h controls the optional stereo headphone out, and Register 06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at -dB. ML5 to ML0 is for left channel level, MR5 to MR0 is for the right channel and MM5 to MM0 is for the mono out channel. Support for the MSB of the volume level is not provided by the WM9707. If the MSB is written to, then the WM9707 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a 1xxxxx the WM9707 interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value written to it. The driver can use this feature to detect if support for the 6th bit is there or not. The default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000), which corresponds to 0dB gain with mute on.
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MUTE 0 0 0 1 MX4...MX0 (BINARY) 0 0000 0 0001 1 1111 x xxxx FUNCTION 0dB attenuation 1.5dB attenuation 46.5dB attenuation
Production Data
dB attenuation
Table 5 Volume Register Function
MASTER TONE CONTROL REGISTERS (INDEX 08h)
Optional register for support of tone controls (bass and treble). The WM9707 does not support bass and treble and writing to this register will have no effect, reading will result in all zeros.
PC BEEP REGISTER (INDEX 0Ah)
This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at -dB. WM9707 defaults to the PC-beep path being muted, except during reset when the path is open, so an external speaker should be provided within the PC to alert the user to power on self-test problems. MUTE 0 0 1 PV3...PV0 (BINARY) 0000 1111 xxxx FUNCTION 0dB attenuation 45dB attenuation
dB attenuation
Table 6 PC-beep Register Function
ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 0Ch - 18h AND 72h)
This controls the gain/attenuation for each of the analogue inputs and mixer PGA. Each step corresponds to approximately 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at -dB.
REGISTER 0Eh (MIC VOLUME REGISTER)
This has an extra bit that is for a 20dB boost. When bit 6 is set to 1 the 20dB boost is on. The default value is 8008h, which corresponds to 0dB gain with mute on. The default value for the mono registers is 8008h, which corresponds to 0dB gain with mute on. The default value for stereo registers is 8808h, which corresponds to 0dB gain with mute on. MUTE 0 0 0 1 GX4...GX0 (BINARY) 00000 01000 11111 xxxxx FUNCTION +12dB gain 0dB gain -34.5dB gain -dB gain
Table 7 Mixer Gain Control Register Function
RECORD SELECT CONTROL REGISTER (INDEX 1Ah)
Used to select the record source independently for right and left (see Table 8). The default value is 0000h, which corresponds to Mic in.
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SR2 TO SR0 0 1 2 3 4 5 6 7 RIGHT RECORD SOURCE Mic CD in (R) Video in (R) Aux in (R) Line in (R) Stereo mix (R) Mono mix Phone SL2 TO SL0 0 1 2 3 4 5 6 7 Mic CD in (L) Video in (L) Aux in (L) Line in (L) Stereo mix (L) Mono mix Phone
Production Data LEFT RECORD SOURCE
Table 8 Record Select Register Function
RECORD GAIN REGISTERS (INDEX 1Ch)
1Ch is for the stereo input and 1Eh is for the optional special purpose correlated audio Mic channel. Each step corresponds to 1.5dB. 22.5dB corresponds to 0F0Fh. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel(s) is set at -dB. The default value is 8000h, which corresponds to 0dB gain with mute on. MUTE 0 0 1 GX3...GX0 (BINARY) 1111 0000 xxxxx FUNCTION +22.5dB gain 0dB gain -dB gain
Table 9 Record Gain Register Function
GENERAL PURPOSE REGISTER (INDEX 20h)
This register is used to control several miscellaneous functions of the WM9707. Below is a summary of each bit and its function. Only the 3D, MIX, MS and LPBK bits are supported by the WM9707. The MS bit controls the Mic selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-link, allowing for full system performance measurements. The function default value is 0000h which is all off. BIT POP ST 3D LD LLBK RLBK MIX MS LPBK FUNCTION PCM out path and mute, 0 = pre-3D, 1 = post-3D Simulated stereo enhancement, on/off 1 = on 3D stereo enhancement on/off, 1 = on Loudness (bass boost) on/off, 1 = on Local loop back - for modem, line CODEC Remote loop back - for modem, line CODEC Mono output select 0 = Mix, 1 = Mic Mic select 0 = Mic1, 1 = Mic2 ADC/DAC loopback mode WM9707 SUPPORT Yes No Yes No No No Yes Yes Yes
Table 10 General Purpose Register Function
3D CONTROL REGISTER (INDEX 22h)
This register is used to control the centre and/or depth of the 3D stereo enhancement function built into of the AC'97 component. Only the depth bits DP0 to 3 have effect in the WM9707. DP3...DP0 (DECIMAL) 0 1 8 15 100% PD Rev 4.1 June 2006 26 Typical value DEPTH 0%
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POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)
Production Data
This read/write register is used to program Powerdown states and monitor subsystem readiness. The lower half of this register is read only status, a 1 indicating that the subsection is ready. Ready is defined as the subsection able to perform in its nominal state. When this register is written the bit values that come in on AC-link will have no effect on read only bits 0 to 7. When the AC-link CODEC Ready indicator bit (SDATAIN slot 0, bit 15) is a 1 it indicates that the AClink and the WM9707 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any, are ready. READ BIT REF ANL DAC ADC FUNCTION VREFs up to nominal level Analogue mixers, etc ready DAC section ready to accept data ADC section ready to transmit data
Table 11 Powerdown Status Register Function The powerdown modes are as follows. The first three bits are to be used individually rather than in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. PR0 and PR1 control the PCM ADCs and DACs only. PR6 is not supported by the WM9707. WRITE BIT PR0 PR1 PR2 PR3 PR4 PR5 PR6 EAPD FUNCTION PCM in ADCs and input Mux Powerdown PCM out DACs Powerdown Analogue mixer Powerdown (VREF still on) Analogue mixer Powerdown (VREF off) Digital interface (AC-link) Powerdown (external clock off) Internal clock disable HP amp Powerdown - not supported External amplifier Powerdown
Table 12 Powerdown Control Register Function
PR0 = 1
PR1 = 1
PR2 = 1
PR4 = 1
NORMAL
ADCs OFF PR0
DACs OFF PR1
ANALOGUE OFF PR2 OR PR3
DIGITAL I/F OFF PR4
SHUT OFF CODA LINK
PR0 = 0 AND ADC = 1
PR1 = 0 AND DAC = 1
PR2 = 0 AND ANL = 1
WARM RESET
READY = 1 DEFAULT
COLD RESET
Figure 16 An Example of the WM9707 Powerdown/Powerup Flow Figure 16 illustrates one example procedure to do a complete Powerdown of the WM9707. From normal operation sequential writes to the Powerdown Register are performed to Powerdown the WM9707 a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4) can be executed to shut down the WM9707's digital interface (AC-link).
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Production Data The part will remain in sleep mode with all its registers holding their static values. To wake up the WM9707, the AC'97 controller will send a pulse on the sync line issuing a warm reset. This will restart the WM9707's digital interface (resetting PR4 to 0). The WM9707 can also be woken up with a cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them to their default states. When a section is powered back on, the Powerdown Control/Status Register (index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any operation that requires it.
PR1 = 1
PR2 = 1
PR4 = 1
ADCs OFF PR0
DACs OFF PR1
ANALOGUE OFF PR2 OR PR3
DIGITAL I/F OFF PR4
SHUT OFF CODA LINK
PR1 = 0 AND DAC = 1
PR2 = 0 AND ANL = 1
WARM RESET
Figure 17 The WM9707 Powerdown/Flow with Analogue Still Alive Figure 17 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This is used when the user could be playing a CD (or external LINE_IN source) through WM9707 to the speakers but have most of the system in low power mode. The procedure for this follows the previous except that the analogue mixer is never shut down.
POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)
Note that in order to go into ultimate low power mode, PR4 and PR5 are required to be set which turns off the oscillator circuit. Asserting SYNC resets the PR4 and PR5 bit and re-starts the oscillator in the same was as the AC link is restarted. Note that PR4 is redundant in slave mode.
REVISION 2.1 REGISTERS (INDEX 28h T0 58h)
These registers are specified as to use in Revision 2.1 of the AC'97 specification and have the following functions on the WM9707:
REGISTER 28h - EXTENDED AUDIO ID
The Extended Audio ID register is a read only register that identifies which extended audio features are supported (in addition to the original AC'97 features identified by reading the reset register at index 00h). A non zero value indicates the feature is supported. DATA BIT VRA DRA VRM CDAC SDAC LDAC AMAP ID1 ID0 FUNCTION Variable rate audio support Double rate audio support Variable rate Mic ADC support Centre DAC support Surround DAC support LFE DAC support Slot to front DAC mapping support CODEC configuration - fixed in 9707 CODEC configuration - pin 45 value ANY MODE 1 0 0 0 0 0 0 0 1 (Inverse of level at pin 45)
Table 13 Extended Audio ID Register
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WM9707
Production Data
REGISTER 2Ah - EXTENDED AUDIO STATUS AND CONTROL REGISTER
The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. DATA BIT VRA DRA VRM CDAC SDAC LDAC MADC PRI PRJ PRK PRL FUNCTION Enables variable rate audio mode Enable double rate audio mode Enables variable rate Mic ADC Indicates centre DAC ready Indicates surround DAC ready Indicates LFE DAC ready Indicates Mic ADC ready Set to turn off centre DAC Set to turn off surround DACs Set to turn off LFE DACs Set to turn off Mic ADC READ/WRITE Read/write Read/write Read/write Read Read Read Read Read/write Read/write Read/write Read/write WM9707 SUPPORT Yes No No No No No No No No No No
Table 14 Extended Audio Status and Control Register
REGISTER 2Ch TO 32h - AUDIO SAMPLE RATE CONTROL REGISTERS
These registers are read/write registers that are written to, to select alternative sample rates for the audio PCM converters. Default is the 48ks/s rate. Note that only Revision 2.1 recommended rates are supported by the WM9707, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read back. Note that the SPDIF mode only supports 48ks/s rate.
REGISTERS 36h AND 38h - 6 CHANNEL VOLUME CONTROL
These read/write registers control the output volume of the optional four PCM channels. (not supported by the WM9707)
VENDOR RESERVED REGISTERS (INDEX 5Ah - 7Ah)
These registers are vendor specific. Do not write to these registers unless the Vendor ID register has been checked first to ensure that the driver knows the source of the AC `97 component.
SPDIF DIGITAL AUDIO DATA OUTPUT - (INDEX 5Ch)
The WM9707 provides an SPDIF output. In order to enable this output, bit SPDF in Register 5Ch should be set. Additionally, a bit SCMS in Register 5Ch may also be set, which sets the copyright flag in the IEC958 data, allowing serial copy protect mechanisms to be removed. The WM9707 can be programmed to automute the DACs. By setting the mute bit, the WM9707 will mute the DACs when it detects a continuous sequence of 1024 zeros. Register 5Ch contains four vendor specific control bits. DATA BIT AME SPDE SPDC HPFD FUNCTION Setting this bit enables the automute function which causes the DAC PGAs (Reg 18) to mute when the data input is zero for 1024 bits. Setting this enables the SPDIF output. It can also be enabled by raising the SPDEN pin (Pin 47) to DVDD. This enables the copyright protect bit in the SPDIF data stream. Setting this bit disables the HPF on the ADC path.
Table 15 SPDIF Digital Audio Data Output and Automute Control
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VENDOR SPECIFIC GAIN CONTROL REGISTERS - (INDEX 72h)
Production Data
This register controls the gain and mute functions applied to the mixer path. This PGA is not accommodated in the Intel specification, but is required in order to allow the option of simultaneous recording of the mixer output and playback of DAC signals. The function is as per the other mixer PGA's. However, the default value of the register is not-muted. If it is not used it will be transparent to the user.
VENDOR ID REGISTERS (INDEX 7Ch TO 7Eh)
This register is for specific vendor identification if so desired. The ID method is Microsoft's Plug and Play Vendor ID code. The first character of that ID is F7 to F0, the second character S7 to S0, and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the Vendor Revision number. In the WM9707 the vendor ID is set to WML3. Wolfson is a registered Microsoft Plug and Play vendor.
VENDOR SURROUND SOUND REGISTERS (INDEX 74h)
This register describes how data is mapped to the AC'97 DACs. Register 74h can be used to change the incoming DAC data slots that are used by the on-board DACs. This allows software control of multiple CODECs. SURROUND SOUND DSS1, DSS0 00 01 1X PCM OUT LEFT 3 7 6 PCM OUT RIGHT 4 8 9
Table 16 Vendor Surround Sound Register - Reg 74 [1:0] The volume control register is still 02h and the rate register is 2Ch. The ID pins have no effect on this mapping.
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WM9707 SERIAL INTERFACE REGISTER MAP
Production Data
The following table shows the function and address of the various control bits that are loaded through the serial interface during write operations. Reg 00h 02h 04h 06h Name Reset Master volume LNLVL volume Master volume mono PCBEEP volume Phone volume Mic volume Line in volume CD volume Video volume Aux volume PCM out volume Rec select Rec gain General purpose 3D control Reserved Power/down control status Ext'd audio ID Ext'd audio stat/ctrl Front DAC rate Audio ADC rate Vendor specific D15 X Mute Mute Mute D14 SE4 X X X D13 SE3 X X X D12 SE2 ML4 ML4 X D11 SE1 ML3 ML3 X D10 SE0 ML2 ML2 X D9 ID9 ML1 ML1 X D8 ID8 ML0 ML0 X D7 ID7 X X X D6 ID6 X X X D5 ID5 X X X D4 ID4 MR4 MR4 MM4 D3 ID3 MR3 MR3 MM3 D2 ID2 MR2 MR2 MM2 D1 ID1 MR1 MR1 MM1 D0 ID0 MR0 MR0 MM0 Default 6150h 8000h 8000h 8000h
0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h 26h
Mute Mute Mute Mute Mute Mute Mute Mute X Mute POP X X APD
X X X X X X X X X X X X X X
X X X X X X X X X X 3D X X PR5
X X X GL4 GL4 GL4 GL4 GL4 X X X X X PR4
X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X X PR3
X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X X PR2
X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX X X PR1
X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS X X PR0
X X X X X X X X X X LPBK X X X
X X 20dB X X X X X X X X X X X
X X X X X X X X X X X X X X
PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 X X X X X X
PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 X GR3 X DP3 X REF
PV2 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 X DP2 X ANL
PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 X DP1 X DAC
X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 X DP0 X ADC
8000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 000Fh
28h 2Ah 2Ch 32h 5Ch
ID1 X
ID0 PRL
X PRK
X PRJ
X PRI
X X
Amap Ldac Madc Ldac SR9 SR9 X SR8 SR8 X
Sdac Cdac Sdac Cdac SR7 SR7 X SR6 SR6 X
X X SR5 SR5 X
X X SR4 SR4 X
VRM VRM SR3 SR3
X X SR2 SR2
DRA DRA SR1 SR1
VRA VRA SR0 SR0 AME
1001h 0000h BB80h BB80h 1000h
SR15 SR14 SR13 SR12 SR11 SR10 SR15 SR14 SR13 SR12 SR11 SR10 REVISION X X
HPF D 72h 74h 7Ah 7Ch 7Eh Front mixer volume Mute Surround sound Vendor reserved Vendor ID1 Vendor ID2 X X F7 T7 X X X F6 T6 X X X F5 T5 GL4 X X F4 T4 GL3 X X F3 T3 GL2 X X F2 T2 GL1 X X F1 T1 GL0 X X F0 T0 X X X S7 X X X S6 X X X S5 GR4 X X S4 GR3 X X S3
SPD C GR2 X X S2
SPD E GR1 GR0 0808h 0000h 0000h 574Dh 4C03h
DSS1 DSS0 X S1 X S0 Rev0
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1
Table 17 Serial Interface Register Map Description
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WM9707 RECOMMENDED EXTERNAL COMPONENTS
DVDD AVDD 1
C1 C2
Production Data
DVDD1 DVDD2 DVSS1 DVSS2
AVDD1 AVDD2 AVSS1 AVSS2
25 38
C3 C4
9 4 7
26 42 AGND
DGND
C5 C6 C7 C8 C9 C10
12 13 14 15 16 17 18 19 20 21 22 23 24
PCBEEP PHONE AUXL AUXR VIDEOL VIDEOR CDL CDGND CDR MIC1 MIC2 LINEINL LINEINR LINEOUTL LINEOUTR MONOOUT 35 36 37 39 41 + C25 + C26 + C27 + C28 + C29 AGND CX3D1 CX3D2 33 34
C23 C24
VREF VREFOUT
27 28
C18 C19 C20 +
MIXER INPUTS
CAP2
32
C21 C22 +
C11 C12 C13 C14 C15 C16 C17
AGND
WM9707
AGND
STEREO OUTPUT MONO OUTPUT LINE LEVEL STEREO
MASTER/ SLAVE SELECT
45 AVSS
CID
LNLVLOUTL LNLVLOUTR
5 6
SDATAOUT BITCLK SDATAIN SYNC RESETB XTLIN 2
XT C31 C30
SPDIF ENABLE 44 SPDIF EAPD XTLOUT 3 48 47
R1
AC-LINK
Notes: 1. C1 to C24 should be as close to WM9707 as possible. 2. AGND and DGND should be connected as close to WM9707 as possible. 3. R1 required if driving pin 44 from external control logic. R1 not required when pin 44 is tied directly to DVDD or DVSS.
8 10 11
DGND
Figure 18 External Components Diagram
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WM9707
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 to C4 C5 to C17 C18 C19 C20 C21 C22 C23 C24 C25 to C29 C30 and C31 R1 XT SUGGESTED VALUE 100nF 470nF 1F 0.1F 10F 0.1F 10F 100nF 47nF 10F 22pF 1k 24.576 MHz 3D low pass filter. This value sets nominal 100Hz. 3D high pass filter. This value sets nominal 1kHz. Output AC coupling caps to remove VREF DC level from outputs. Optional capacitors for better crystal frequency stability. See note 3 above DESCRIPTION De-coupling for DVDD and AVDD
Production Data
AC coupling capacitors for setting DC level of analogue inputs to VCAP1. Value chosen to give corner frequency below 20Hz for min 10K input impedance. Reference de-coupling capacitors for ADC, DAC, Mixer and CAP2 references. Ceramic type or similar.
AC'97 master clock frequency. A bias resistor is not required, but if connected will not affect operation if value is large (above 1M).
Table 18 External Component Values
Figure 19 Suggested SPDIF Output Circuit (DVDD = 5V)
RECOMMENDATIONS FOR 3.3V OPERATION
The device's performance with AVDD = 3.3V is shown in Electrical Characteristics. In 3.3V analogue operation, mid-rail reference scales to 1.65V. All ADC and DAC references are 2/3rds of their nominal 5V value. Input and output signals that are 1Vrms in 5V applications, scale to 660mVrms in 3.3V applications. It is not possible to produce an undistorted 1Vrms output by using the mixer PGA gain whilst running from a 3.3V analogue supply.
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WM9707 PACKAGE DIMENSIONS
FT: 48 PIN TQFP (7 x 7 x 1.4 mm) DM003.B
Production Data
b
e
25
36
37
24
E1
E
48
13
1
12
D1 D c
A A2
A1
L
-Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L MIN ----0.05 1.35 0.17 0.09
ccc REF:
0.45 o 0
Dimensions (mm) NOM --------1.40 0.22 ----9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.60 o 3.5
MAX 1.60 0.15 1.45 0.27 0.20
0.75 o 7
Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM9707 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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